Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
In order to improve the usefulness of a PLD, a hardware processor core, such as the PowerPC® processor of IBM Corp. of Armonk, N.Y., can be embedded in the programmable logic, for example, as in the Virtex™-II Pro FPGA from Xilinx, Inc. of San Jose, Calif. The availability of an embedded processor core can significantly increase the efficiency and operating speed of systems implemented in the FPGA containing the core.
Another way of embedding a processor in a PLD design is to implement a “soft processor” that uses the programmable fabric of the PLD itself to implement the processor. For example, the MicroBlaze™ processor core from Xilinx, Inc. is an example of such a software core.
The software for state machines using embedded processors is typically produced using ad-hoc C code techniques, although some formalisms exist. For example, in U.S. Pat. No. 7,131,077 (“Using an Embedded Processor to Implement a Finite State Machine”, which is hereby incorporated herein by reference), James-Roxby and Keller describe a system using an XML (eXtensible Mark-up Language) to specify the required behavior of a state machine. Similarly, the interfacing of the processor to the hardware fabric is normally ad-hoc, although it can be automatically generated as described in U.S. Pat. No. 7,131,077.
It is desirable to provide further formalisms based around state machine interactions and C code, in order to further improve the design process for systems in which state machines are implemented using either hardware or software processor cores, or both hardware and software cores.